1. Field of the Invention
This invention relates generally to floating current mirror circuits, particularly those suitable for manufacturing in bipolar or BiCMOS integrated circuits. More particularly, this invention relates to floating current mirror circuits designed for high impedance output loads.
2. Description of the Prior Art
Current mirrors are typically used in operational amplifier circuit design to repeat currents ratioed to a first referenced current to one or more other locations. This allows the design to use a single reference current to generate additional different currents referenced to each other throughout a circuit as needed.
The basic structure of a current mirror is a diode or diode coupled transistor coupled across the base emitter junction of additional transistors. If the betas of the transistors are sufficiently large, the current through the additional transistors will be substantially proportional to the collector current of the diode coupled transistor by some factor.
In some configurations, the emitter terminals of the transistors and the diode coupled transistor are coupled to a common node. In using this configuration for current sources in integrated circuit designs, it is common to have more than one transistor having a base coupled to the base of the diode coupled transistor and an emitter coupled to the other emitters at the common node. In this fashion the magnitude of the current can be increased by a multiple of the number of additional collectors, or by the ratio of the emitter areas. Alternatively, emitter degeneration resistors may be used so that the current out of the mirror cell is less than the referenced current.
A floating mirror circuit refers to a mirror circuit where the emitters are coupled not to a ground but to a node at a different potential or to a node coupled to the ground by a current source. Examples of such include the floating current mirror circuit disclosed in U.S. Pat. No. 4,366,445 to Cave. This patent discloses a mirror circuit using all NPN transistors to overcome undesirable limited frequency responses of similar circuits employing PNP differential input transistors.
Another example of a floating current mirror includes the LM108 Super Beta Operational Amplifier in the National Data Book which discloses a three transistor mirror circuit with a diode coupled transistor coupled with a current source at the collector and base, and an emitter coupled to a floating node. A second transistor has a collector terminal coupled to a current source, a base coupled to the base and collector of the diode coupled transistor, and an emitter coupled to the floating node. A third transistor has a base terminal coupled to the collector terminal of the second transistor and an emitter coupled to the floating node. The output of this mirror circuit is at the floating node which feeds into the base terminal of a pass element.
An implementation of a floating current mirror circuit is shown in FIG. 1, where a diode coupled transistor 8 is diode coupled having the base and collector are coupled together is shown. The base of transistor 10 is coupled to the base and collector of transistor 8 and the collectors of transistors 8 and 10 are coupled to the current sources 2 and 4 respectively. The base of transistor 12 is coupled to the collector of transistor 10 and the collector of transistor 12 is coupled along with current sources 2 and 4 to a potential such as V.sub.cc at a node 14. The emitters of transistors 8, 10 and 12 are coupled together at a floating node 16 where an output voltage may be taken if the current sources 2 and 4 are, for example, differentially driven by a previous stage. However, this is not necessary. The node 14 is floating because it is coupled above ground at a node 18 by a current source 6. Alternatively, node 16 can be biased above ground by a potential (not shown).
The output of the circuit may be taken at the floating node 16 when a load having an impedance or capacitance is coupled thereto (not shown). However, the output of the floating mirror of the prior art at the floating node has a substantially lower output impedance than high impedance loads such as operational amplifiers and field effect transistors. Loading the prior art voltage output at the floating node requires the insertion of a voltage buffer to match the impedances of the output at the floating node and the input of the load. Inserting a voltage buffer at the floating node may add a capacitance that results in an addition of a pole to the circuit. The additional pole causes frequency instability at the output that can result in undesirable oscillations or decreased circuit performance at higher frequencies. Furthermore, the addition of a voltage buffer contributes to power dissipation resulting from the additional impedance inserted into the circuit and may also add noise.
Additionally, there are problems with inserting a floating mirror cell, such as that shown in FIG. 1, into a chip due to insufficient head room to accommodate the cell in low voltage power supply circuits such as 3.3 volt DC circuits. If V.sub.cc is only 3.3 volts above ground, then the floating node 16 must be at least one V.sup.BE +V.sub.SAT below V.sub.cc, so at most, the permissible output excursion for the node 16 is about 2.3 volts. Therefore, there are a number of drawbacks in the prior art.